VLSI Design Automation
Instructor: Prof. Shantanu Dutt
Important Notes : -
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- Intro. Lecture Notes # 1 ps
pdf
- Intro. Lecture Notes # 2 -- VLSI Design Flow (hardcopy)
- Lecture Notes # 3 -- High Level Synthesis (hardcopy)
- Lecture Notes # 3b -- High Level Synthesis (courtesy of and copyrighted by Prof. Kia Bazargan) ppt
- Lecture Notes # 3c -- Register Allocation in High Level Synthesis pdf
- Lecture Notes # 4 -- Chip Layout Styles (hardcopy)
- Lecture Notes # 5 -- VLSI Circuit Issues (no notes, actually :-(. But was done in class).
- Lecture Notes # 6 -- Partitioning (probability based) ps
pdf
- PROP Papers:
Conference version: S. Dutt and W. Deng, ``A probability-based approach to VLSI circuit partitioning'', Proc. Design Automation Conference, June 1996, pp. 100-105.
Journal version: S. Dutt and W. Deng, ``Probabilistic Approaches to VLSI Circuit Partitioning'', IEEE Trans. CAD, Vol. 19, No. 5, May 2000, pp. 534-549. ps(gzipped) , or pdf , or
Print version only for teaching purpose: pdf
- Lecture Notes # 7 -- Multilevel Partitioning - Hmetis ppt
- Lecture Notes # 8 -- Algorithmic Techniques in VLSI CAD ppt
- Floorplanning intro, simulated annealing and mixed integer programming formulation (from Prof. Hai Zhou's web site at NWU) pdf
- Yet another (good) FP slide set pdf
- Sequence-pair based floorplanning technique: (courtesy of Karthik Chandramouli) pdf
- Intro to placement and basic PDP approach and rationale (hard copy)
- Quadratic Placement: quadratic and linear WL objectives ppt , pdf
- Classical placement algorithms (min-cut, simulated annealing) pdf
- Simultaneous level partitioning based PDP: ppt
- General and Channel Routing: ppt
- Maze and Line Routing: pdf
- Global Routing: pdf
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