High Performance Communication
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| Topic/Slides | Assigned Paper/Notes |
| | |
| no class (HotI 06) | |
| M. Venkatachalam, P. Chandra, R. Yavatkar, A Highly Flexible, Distributed Multiprocessor Architecture for Network Processing, Computer Networks, 2003 Intel Architecture presentation | |
| no class -- Labor Day | |
| TBP Homework 2 out | |
| Petrini et al., Scalable Collective Communication on the ASCI Q Machine Boden et al., Myrinet: A Gigabit-per-second Local Area Network J. Liu, et al, Performance Comparison of MPI Implementations over InfiniBand, Myrinet and Quadrics | |
| no class | Homework 2 due 9/22 |
| Stargen, PCI Express and Advanced Switching: Evolutionary Path to Building Next Generation Interconnects Project Proposal Due | |
| Allyn Romanow, Stephen Bailey, RDMA over IP Hyong-youb Kim and Scott Rixner, TCP Offload through Connection Handoff, EuroSys 06 | |
| K. Mackenzie, An Intel IXP1200-based Network Interface D.K. Panda, Can User Level Protocols Take Advantage of Multi-CPU NICs? | |
| Brightwell, Initial Performance Evaluation of the Cray SeaStar Interconnect (hoti05), (micro06) Portals 3.0 | |
| no class (IXA Summit 06) | |
| no class - Fall Recess | |
| Structuring application communication: MPI, PVM ECho stack (Arvind K.) | Introduction to MPI ECho & EVpath Project Update Report Due |
| Himanshu Raj, Ivan Ganev, Karsten Schwan, Jimi Xenidis, Scalable I/O Virtualization via Self-Virtualizing Devices Liu et al, High Performance VMM-Bypass I/O in Virtual Machines, USENIX Annual Technical Conference 2006 | |
| Programmable networking, Click (Priyanka T.) | Campbell A.T., De Meer H.G., Kounavis M.E., Miki K., Vicente J., and Villela D., A Survey of Programmable Networks Robert Morris, Eddie Kohler, John Jannotti and M. Frans Kaashoek, The Click Modular Router |
| Network Processor Survey | |
| Caching in NPs NP Design Analysis (Ranjith S.) | J. Mudigonda, H. M. Vin and R. Yavatkar, A Case for Data Caching in Network Processors Ramaswamy et al., Application Analysis and Resource Mapping for Heterogeneous Network Processor Architectures, NP3, 2004 T. Wolf, Performance Models for Network Processor Design, TPDS |
| IBM Cell (Vishakha G.) | |
| Reconfigurable Hardware, FPGAs (Jeff Y.) Applications: IDS on FPGAs (Gregory D.) | David E. Taylor, Jonathan S. Turner, John W. Lockwood, Dynamic Hardware Plugins (DHP): Exploiting Reconfigurable Hardware for High-Performance Programmable Routers Chris Clark, Scalable Pattern Matching for High Speed Networks |
| Applications: Classification, Scheduling, Multicast, DHTs, Content Processing | Francis Chang, Wu-chang Feng, Wu-chi Feng, Kang Li, Efficient Packet Classification with Digest Caches, NP3 Laxmi Bhuyan's group research, An Efficient Packet Scheduling Algorithm in Network Processors Design and Implementation of a Content Aware Switch using a Network Processor |
| no class - Thanksgiving | |
| Tools: Benchmarks (Matt K.) | Byeong Kil Lee, Lizy Kurian John, NpBench: A Benchmark Suite for Control plane and Data plane Applications for Network Processors, Int't Conf. on Computer Design, 2003 NetBench, CommBench |
| Tools: simulators and development Compiler support (Fernando A.) | Y. Luo, L. Bhuyan, NePSim: A Network Processor Simulator with Power Evaluation Framework, IEEE Micro, Special Issue on Network Processors, September/October 2004 Herbert Bos, et al., FFPF: Fairly Fast Packet Filters Harrick M. Vin, Jayaram Mudigonda, Jamie Jason, Erik J. Johnson, Roy Ju, Aaron Kunze, and Ruiqi Lian, Shangri-La: A Programming Environment for Packet-processing Systems: Design Considerations |
| Project Presentations | Matt, Jeff, Arvind, Ranjith, Adit |
| Project Presentations | Priyanka, Vishakha, Gregory, Purav, Rao, Fernando |
| | Project Due |
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