| Lecture | Topic | Format | |||
| HTML | PDF-2 | PDF-4 | PDF-6 | ||
| Lecture 1 | Introduction | ||||
| Lecture 2 | Introduction to Logic Circuits: Variables, functions, truth tables, gates and networks | ||||
| Lecture 3 | Introduction to Logic Circuits: Boolean algebra | ||||
| Lecture 4 | Introduction to Logic Circuits: Synthesis using AND, OR, and NOT gates | ||||
| Lecture 5 | Introduction to Logic Circuits: Design Examples | ||||
| Lecture 6 | Introduction to Logic Circuits: CAD Tools and VHDL | ||||
| Lecture 7 | Optimized Implementation of Logic Functions: Karnaugh Maps and Minimum Sum-of-Product Forms | ||||
| Lecture 8 | Optimized Implementation of Logic Functions: Strategy for Minimization, Minimum Product-of-Sums Forms, Incompletely Specified Functions | ||||
| Lecture 9 | Optimized Implementation of Logic Functions: Multiple Output Circuits, NAND and NOR Logic Networks | ||||
| Lecture 10 | Implementation Technology: Standard Chips and Programmable Logic Devices | ||||
| Lecture 11 | Implementation Technology: Look-up Tables, XOR and XNOR gates | ||||
| Lecture 12 | Implementation Technology: Buffers, Tri-state gates, Transmission gates | ||||
| Lecture 13 | Implementation Technology: NMOS and PMOS Transistors, CMOS logic gates | ||||
| Lecture 14 | Optimized Implementation of Logic Functions: Multilevel Synthesis and Analysis | ||||
| Lecture 15 | Optimized Implementation of Logic Functions: Multilevel Synthesis and Analysis | ||||
| Lecture 16 | Number Representation and Arithmetic Circuits: Number Representation and Unsigned Addition | ||||
| Lecture 17 | Number Representation and Arithmetic Circuits: Signed Numbers, Binary Adders and Subtractors | ||||
| Lecture 18 | Number Representation and Arithmetic Circuits: Fast Adder Designs, Tradeoffs, and Examples | ||||
| Lecture 19 | Number Representation and Arithmetic Circuits: Design of Arithmetic Circuits Using CAD Tools | ||||
| Lecture 20 | Number Representation and Arithmetic Circuits: Other Number Representations | ||||
| Lecture 21 | Combinatorial | ||||
| Lecture 22 | Combinatorial | ||||
| Lecture 23 | Combinatorial | ||||
| Lecture 24 | Flip-Flops, Registers and Counters: Latches | ||||
| Lecture 25 | Flip-Flops, Registers and Counters: Flip-Flops | ||||
| Lecture 26 | Flip-Flops, Registers and Counters: Registers and Counters | ||||
| Lecture 27 | Synchronous Sequential Circuits: State Diagrams, State Tables | ||||
| Lecture 28 | Synchronous Sequential Circuits: Implementations using D-type, T-type and JK-type Flip-Flops | ||||
| Lecture 29 | Synchronous Sequential Circuits: State Assignment Problem, Mealy State Machines | ||||
| Lecture 30 | VHDL for Sequential Circuits | ||||
| Lecture 31 | Design of | ||||
| Lecture 32 | State Minimization | ||||
Digital Logic Lectures PPT
