High-Performance Computer Architecture
Instructor: Prof. Hyesoon Kim
Course Description :
This is a graduate-level course on how the computer works. In this
course, we will review fundamental structures in modern microprocessor
and computer system architecture design. We will cover computer
organization, instruction set design, memory system design, pipelining,
cache coherence protocols, memory schedulers, power/energy, prefetching
and other techniques to explore instruction level parallelism and
thread level parallelism. We will also cover system level topics such as
storage subsystems. We will also have case studies as to how modern
microprocessors are designed.
Text book:
No required text book.
Recommended books
Computer Architecture: A Quantitative Approach, 4th Edition by John Hennessy and David Patterson.
Microprocessor architecture, Jean-Loup Baer, Cambridge.
Download slides
No | Topics | Readings | ||
1 | Course introduction, Metrics, Review pipeline | H&P AppA/Ch1 or Baer Ch1/Ch2 | ||
Simulation, PA #1 | ||||
2 | Dependences | H&P Ch2/Ch3 or Baer Ch3 | ||
register renaming | ||||
3 | Out-of-order processor, instruction scheduling and commit | H&PCh2/Ch3,Baer Ch3.1-Ch3.3 [MA1][MA2] | ||
Branch prediction | ||||
4 | Branch prediction | H&PCh2, BaerCh4, [BP1][BP2] | ||
5 | cache DRAM | AppC | ||
H&PCh5, [CAC1][CAC2] BaerCh6 | ||||
6 | Guest Lecture: Joe Bungo (ARM) | |||
7 | Memory-II | |||
8 | prefetcher | [MEMSCH1][MEMSCH2] | ||
9 | Guest lecture (10/20) | [PREF] | ||
10 | Multi-processors and multi-threading, MIS Cache coherence | H&P Ch.4, Baer Ch.8 | ||
11 | Multi-cores and cache coherence Synchronization, consistency | Ch4,[SC] | ||
Ch 4, [MC] | ||||
12 | Introduction to GPUs | |||
[TES] | ||||
13 | interrupts&exceptions , Power | H&P Ch2, H&P AppG, [PRED][INT][PWR1][PWR2][PWR3] | ||
14 | 11/22,11/24 | Static Instruction Scheduling | Thanksgivig Holidays(11/24) | |